AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents Device Power-Up

Power-Up and Power-Down Sequencing

Cyclone® V/ Arria® V SoC devices have the following additional power rails to consider for power sequencing.


Refer to "Power-Up Sequence" in the "Power Management" chapter of Volume 1: Device Interfaces and Integration in the Cyclone® V or Arria® V Device Handbook.

GUIDELINE: Consider ramp times for maximum transient currents on supplies when designing the Power Distribution Network (PDN).

When using the PDN Tool to calculate the required target impedance of your application’s PDN for the core fabric’s VCC supply, model the ramp time of the maximum transient current on VCC using the Core Clock Frequency and Current Ramp Up Period parameters. This procedure relaxes the target impedance requirements relative to the default step function analysis, resulting in a more efficient PDN with fewer decoupling capacitors.

Initial transient current estimates can be obtained from the EPE Spreadsheet, and more accurate analysis is possible with the Power Analyzer Power Analysis Tool in Intel® Quartus® Prime when your design is closer to completion.

Refer to AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design.