AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

4.4. Boundary Scan for HPS

GUIDELINE: Ensure that the HPS is powered up and held in reset before performing a boundary scan test of the FPGA and HPS I/O.

The HPS JTAG does not support boundary scan tests (BST). To perform boundary scan testing on HPS I/O pins, you must use the FPGA JTAG.