AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents
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3.7. IP Debug Tools

The Intel® Quartus® Prime Design Software includes many IP and system-level debug tools used in FPGA hardware designs.

The following tools are commonly used for system and IP debug in embedded systems:
  • Signal Tap - On-chip logic analyzer constructed from FPGA resources
  • Bus functional models
    • Avalon-MM v2 protocol
    • AXI* v3 protocol
  • System console - Services-based API for controlling soft logic and moving data to/from the FPGA
Each debug tool is introduced at different stages of the hardware design. In a typical hardware design flow, the developer follows these high-level verification steps:
  1. IP Creation in RTL
  2. Testbench and BFM verification of the IP
  3. In silicon testing of the IP using system console to drive stimuli into memory-mapped or streaming interface
  4. In silicon testing of the IP using low level software run on the processor in the HPS

In the case of Signal Tap and system console, if both use the FPGA JTAG interface to communicate data then they can be used simultaneously. For example, you may instrument a trigger condition in Signal Tap and cause the trigger condition to occur via the JTAG-to-Avalon bridge IP controlled by System console. These tools are also capable of being used simultaneously with the HPS tools that communicate over JTAG.

There are two JTAG interfaces on the Cyclone® V/ Arria® V SoC device. The first interface is connected to the FPGA side of the device, while the second interface is connected to the HPS debug access port (DAP).