AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents
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3.2.1. HPS Pin Assignment Design Considerations

Because the HPS contains more peripherals than can all be connected to the HPS Dedicated I/O, the HPS component in Platform Designer (Standard) offers pin multiplexing settings as well as the option to route most of the peripherals into the FPGA fabric. Any unused pins for the HPS Dedicated I/O with loaner capability meanwhile can be used as general purpose I/O by the FPGA.
Note: You can safely ignore the msr.dcts register value changes if you are not configuring the PIN MUX to connect the UART CTS signal.
Note: HPS I/O Bank can only support a single supply of either 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V power supply, depending on the I/O standard required by the specified bank. 1.35V is supported for HPS Row I/O bank only.

GUIDELINE: Ensure that you route USB, EMAC and Flash interfaces to HPS Dedicated I/O first, starting with USB.

Intel recommends that you start by routing high speed interfaces such as USB, Ethernet, and flash to the HPS Dedicated I/O first. USB must be routed to HPS Dedicated I/O because it is not available to the FPGA fabric. The flash boot source must also be routed to the HPS dedicated I/O (and not any FPGA I/O) since these are the only I/Os that are functional before the FPGA I/Os have been configured.

Note: For Cyclone® V SoC U19 package (484 pin count) only one USB controller (instead of two) is usable due to reduced number of available HPS I/O. For more information, refer to Why can't I map USB0 to HPS IO in my Cyclone V SoC U19 package (484 pin count)? in the Knowledge Base.

GUIDELINE: Enable the HPS GPI pins in the Platform Designer (Standard) HPS Component if needed

By default, the HPS GPI interface is not enabled in Platform Designer (Standard). To enable this interface, you must select the checkbox "Enable HLGPI interface" in the Platform Designer (Standard) HPS Component for Cyclone® V/ Arria® V. These pins are then exposed as part of the Platform Designer (Standard) HPS Component Conduit Interface and can be individually assigned at the top level of the design.