AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents Adapting to RGMII

It is possible to adapt the GMII HPS EMAC PHY signals to an RGMII PHY interface at the FPGA I/O pins using logic in the FPGA. While it is possible to design custom logic for this adaptation, this section describes using Platform Designer (Standard) adapter IP.

GUIDELINE: Use the GMII-to-RGMII Adapter IP available in Platform Designer (Standard).

Configure the HPS component in Platform Designer (Standard) for an EMAC as “FPGA” I/O instance. Do not export the resulting HPS component GMII signals in Platform Designer (Standard). Instead, add the Intel® HPS GMII to RGMII Converter to the Platform Designer (Standard) subsystem and connect to the HPS component’s GMII signals. The GMII to RGMII Converter uses the Intel® HPS EMAC Interface Splitter in Platform Designer (Standard) to split out the emac conduit from the HPS component for use by the GMII to RGMII Converter. See the Embedded Peripherals IP User Guide for information on how to use the Intel® HPS GMII to RGMII Converter.

GUIDELINE: Provide a glitch-free clock source for the 10/100 Mbps modes.

In an RGMII PHY interface, the TX_CLK is always sourced by the MAC, but the HPS component’s GMII interface expects TX_CLK to be provided by the PHY device in 10/100 Mbps modes. The GMII to RGMII adaptation logic must provide the 2.5/25 MHz TX_CLK on the GMII’s emac[0,1]_tx_clk_in input port, and the switch between 2.5 MHz and 25 MHz must be accomplished in a glitch-free manner as required by the HPS EMAC. An FPGA PLL can be used to provide the 2.5 MHz and 25 MHz TX_CLK along with an ALTCLKCTRL block to select between counter outputs glitch-free.

Note: Refer to the Cyclone® V RGMII Example Design for hardware and software example of this implementation.