AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

4.5.8. SPI Interface Design Guidelines

GUIDELINE: Consider routing SPI slave signals to FPGA fabric

Due to an erratum in the Cyclone® V/ Arria® V SoC device, the SPI output enable is not connected to the SPI HPS pins. As a result, the HPS SPIS_TXD pin cannot be tri-stated by setting the slv_oe bit (bit 10) in the ctrlr0 register to 1.

Routing the SPI Slave signals to FPGA exposes the output enable signal and allows you to connect it to an FPGA tri-state pin.

GUIDELINE: If your SPI peripheral requires the SPI master slave select to stay low during the entire transaction period, consider using GPIO as slave select, or configure the SPI master to assert slave select during the transaction.

By default, the SPI master is configured with ctrlr0.scph = 0 and ctrlr0.scpol = 0, which makes the Cyclone V or Arria V HPS SPI master deassert the slave select signal between each data word. Set ctrlr0.scph to 1 and ctrlr0.scpol to 1, to make the SPI master assert slave select for the entire duration of the transfer.

Alternatively, consider routing the SPI master peripheral to FPGA, and using GPIO to control the slave select signal.

Note: If you use this method, refer to the following Knowledge Base articles: