AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.4.3. Integrating the HPS EMIF with the SoC FPGA Device

Consider the following when integrating the Cyclone® V or Arria® V SoC HPS EMIF with the rest of the SoC system design.

GUIDELINE: Follow the guidelines for optimizing bandwidth for all masters accessing the HPS SDRAM

Accesses to SDRAM connected to the HPS EMIF go through the L3 Interconnect (except for FPGA-to-SDRAM bridge). When designing and configuring high bandwidth DMA masters and related buffering in the FPGA core, refer to DMA Considerations. The principles covered in that section apply to all high bandwidth DMA masters (for example DMA controller components, integrated DMA controllers in custom peripherals) and related buffering in the FPGA core that access HPS resources (for example HPS SDRAM) through the FPGA-to-SDRAM and FPGA-to-HPS bridge ports, not just tightly-coupled HPS hardware accelerators.