AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.4.2. HPS SDRAM I/O Locations

The Cyclone® V and Arria® V SoC HPS External Memory Interface I/O locations are fixed, depending on the type of memory used. You can refer to the device Pin Out files, under the “HMC Pin Assignment for DDR3/DDR2” and “HMC Pin Assignment for LPDDR2” for exact I/O pins used by the respective memory interface pins.

Note: Unused HPS External Memory Interface I/O Pins cannot be assigned to HPS Peripherals, or used by the FPGA as Loaner IO.
Note: The smallest Cyclone® V SoC package U19 (484 pin count) has narrower HPS SDRAM width (32-bit) compared to larger packages (40-bit). Refer to the "External Memory Interfaces in Cyclone® V Devices" chapter in Cyclone V Device Handbook Volume 1: Device Interfaces and Integration for more information.