AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

1.1. The SoC FPGA Designer’s Checklist

Table 1.  The SoC FPGA Designer's Checklist
Step Title Links Check (X)
HPS Designer's Checklist for SoC FPGAs
Start your SoC FPGA Design here Start your SoC-FPGA design here  
Determining your SoC FPGA Topology  
Design Considerations for Connecting Device I/O to HPS Peripherals and Memory HPS Pin Assignment Design Considerations  
HPS I/O Settings: Constraints and Drive Strengths  
HPS Clocking and Reset Design Considerations HPS Clock Planning  
Early Pin Planning and I/O Assignment Analysis  
Pin Features and Connections for HPS JTAG, Clocks, Reset and PoR  
Internal Clocks  
HPS EMIF Design Considerations Considerations for Connecting HPS to SDRAM  
HPS SDRAM I/O Locations  
Integrating the HPS EMIF with the SoC FPGA Device  
HPS Memory Debug  
DMA Considerations Choosing a DMA Controller  
Optimizing DMA Master Bandwidth through HPS Interconnect  
Timing Closure for FPGA Accelerators  
Managing Coherency for FPGA Accelerators Cache Coherency  
Coherency between FPGA Logic and HPS: Accelerator Coherency Port (ACP)  
Data Size Impacts ACP Performance  
FPGA Access to ACP via AXI or Avalon-MM  
Data Alignment for ACP and L2 Cache ECC accesses  
IP Debug Tools IP Debug Tools  
Board Designer's Checklist for SoC FPGAs
HPS Power Design Considerations Early System and Board Planning  
Early Power Estimation  
Design Considerations for HPS and FPGA Power Supplies for SoC FPGA devices  
Pin Connection Considerations for Board Designs  
Device Power-Up  
Power Analysis and Optimization  
Boundary Scan for HPS Boundary Scan for HPS  
Design Guidelines for HPS Interfaces HPS EMAC PHY Interfaces  
USB Interface Design Guidelines  
QSPI Flash Interface Design Guidelines  
SD/MMC and eMMC Card Interface Design Guidelines  
NAND Flash Interface Design Guidelines  
UART Interface Design Guidelines  
I2C Interface Design Guidelines  
SPI Interface Design Guidelines  
Embedded Software Designer's Checklist for SoC FPGAs
Assemble the components of your Software Development Platform Assembling the Components of Your Software Development Platform  
Golden Hardware Reference Design  
Select an Operating System (OS) for your application Linux or RTOS  
Bare Metal  
Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes  
Assemble your Software Development Platform for Linux Golden System Reference Design (GSRD) for Linux  
GSRD for Linux Development Flow  
GSRD for Linux Build Flow  
Linux Device Tree Design Considerations  
Assemble your Software Development Platform for Bare-metal Application Assembling a Software Development Platform for a Bare-Metal Application  
Assemble your Software Development Platform for Partner OS/RTOS Application Assembling your Software Development Platform for a Partner OS or RTOS  
Choose the Boot Loader Software Choosing Boot Loader Software  
Selecting Software Tools for Development, Debug and Trace Select Software Build Tools  
Select Software Debug Tools  
Select Software Trace Tools  
Board Bring Up Considerations Board Bring Up Considerations  
Boot and Configuration Design Considerations Boot Design Considerations  
Flash Device Driver Considerations Flash Device Driver Design Considerations  
HPS ECC Design Considerations HPS ECC Design Considerations  
HPS SDRAM Considerations HPS SDRAM Considerations