AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

4.5.1. HPS EMAC PHY Interfaces

When configuring an HPS component for EMAC peripherals within Platform Designer (Standard), you must select from one of the following supported PHY interfaces for each EMAC instance:
  • Reduced Gigabit Media Independent Interface (RGMII) using dedicated I/O
  • Media Independent Interface (MII) interface to FPGA fabric
  • Gigabit Media Independent Interface (GMII) interface to FPGA fabric

Any combination of supported PHY interface types can be configured across multiple HPS EMAC instances.

GUIDELINE: For RGMII using HPS Dedicated I/O, develop an early I/O floor-​planning template design to ensure that there are enough HPS Dedicated I/O to accommodate the chosen PHY interfaces in addition to other HPS peripherals planned for HPS Dedicated I/O usage.

Note: For guidelines on configuring the HPS component, refer to the "Introduction to the HPS Component" chapter of the Cyclone® V or Arria® V Hard Processor System Technical Reference Manual.

It is possible to adapt the MII/GMII PHY interfaces exposed to the FPGA fabric by the HPS component to other PHY interface standards—such as RMII, RGMII, SGMII, MII and GMII—by using soft adaptation logic in the FPGA and features in the general-purpose FPGA I/O and transceiver FPGA I/O.

GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers; PHY devices that offer the skew control feature; and device driver availability.

Note: Refer to the device drivers available for your OS of choice or the Linux device driver provided with the Cyclone® V/ Arria® V SoC development kit (Golden System Reference Design)

The Cyclone® V/ Arria® V SoC Hard Processor System (HPS) can connect its embedded Ethernet MAC (EMAC) PHY interfaces directly to industry standard Gigabit Ethernet PHYs using the RGMII interface at any supported I/O voltage using the HPS Dedicated I/O pins. These voltages typically include 1.8V, 2.5V and 3.0V. If the HPS Dedicated I/O pins are used for the PHY interface, then no FPGA routing resources are used and timing is fixed, simplifying timing on the interface. This document describes the design guidelines for RGMII, the most typical interfaces.

You can also connect PHYs to the HPS EMACs through the FPGA fabric using the GMII and MII bus interfaces for Gigabit and 10/100 Mbps access respectively. A GMII-to-SGMII adapter is also available to automatically adapt to transceiver-based SGMII optical modules.

Note: Due to an erratum in the Cyclone® V/ Arria® V SoC device, the RMII PHY interface is not supported when routing through the HPS Dedicated I/O. RMII interface however is supported when routing through the FPGA fabric.