AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.6. Managing Coherency for FPGA Accelerators

Data shared between the HPS and the FPGA logic can be modified at any time, by either the HPS or the FPGA. Many applications require data coherency, which means that changes are propagated throughout the system, so that every master accesses the most up-to-date data value.

When you design for data coherency, first you must determine which data transfers need to be coherent. By default all access between the FPGA and HPS are assumed to be non-coherent unless coherency is explicitly managed by software or using coherent hardware features of the HPS (SCU and ACP).

To determine if peripherals in the FPGA need coherent access to HPS memory, answer the follow questions:
  • Does the MPU need to access data generated by my FPGA peripheral?
  • Does the FPGA peripheral need to access data generated by the MPU?

If the answer to either question is "Yes", the data must be coherent. You can use the ACP to keep the FPGA coherent with cacheable data in the HPS.

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