AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents
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3.5.2. Optimizing DMA Master Bandwidth through HPS Interconnect

FPGA DMA masters have access to HPS resources through the FPGA-to-HPS Bridge and FPGA-to-SDRAM Interface, configurable in the HPS Platform Designer (Standard) Component. The HPS SDRAM controller multi-port-front end (MPFE) provides arbitration for these resources and enforce Quality of Service (QoS) settings. When planning for and designing DMA masters and related buffering that access resources through the HPS interconnect, study the architecture of the HPS interconnect and consider the following guidance and resources available for optimizing bandwidth through the interconnect.

GUIDELINE: Utilize the Cyclone® V FPGA-to-HPS Bridge Design Example to tune for performance

The Cyclone® V FPGA-to-HPS Bridge Design Example is a useful platform for modeling specific data traffic access patterns between the FPGA and HPS resources.

The example design includes a utility that can select the datapaths between endpoints, select transaction characteristics (for example, burst lengths), and report transfer bandwidth. This utility runs on the ARM Cortex* A-9 processor in the HPS.