AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.4.5. HPS Address Mirroring

The Cyclone® V and Arria® V HPS EMIF support address mirroring. This feature can be turned on under the Memory Initialization Options sub-window in the Memory Parameters tab under the Interface Type sub-window of the DDR3 SDRAM Controller with UniPHY GUI. For example, for four chip selects, enter 1011 to mirror the address on chip select #3, #1,and #0.

For more information about address mirroring, refer to External Memory Interface Handbook, Volume 1: Introduction and Specifications.
Figure 4. HPS Address Mirroring