AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents Boot Source

GUIDELINE: Determine which boot source is to be supported.

The HPS side of the Cyclone® V SoC / Arria® V SoC can be booted from a variety of sources, as selected by the BSEL pins:
  • SD/MMC Flash
  • QSPI Flash
  • NAND Flash
  • FPGA Fabric
Each possible boot source has its own strengths:
  • SD cards are cheap, universally available, and have large storage capacities. Industrial versions available, with improved reliability. They are managed NAND flash, so wear leveling and bad block management are performed internally.
  • eMMC devices have smaller packages, are available in large capacities, and can be more reliable than SD. They are not removable, with can be a plus, allowing a more rugged operation.
  • QSPI devices are very reliable, typically with a minimum 100,000 cycles of erase cycles per sector. However, they have less capacity than the other options. They are typically used as a boot source, but not as an application filesystem.
  • NAND devices are available in large sizes, but they are unmanaged NAND, which means that techniques such as wear leveling and bad block management need to be implemented in software.
  • FPGA boot allows HPS to boot without the need of an external Flash device. The FPGA boot memory can be synthesized our of FPGA resources (typically pre-initialized embedded memory blocks) or can be memory connected to the FPGA such as an external SRAM or SDRAM. To boot from FPGA, the FPGA must be configured using a traditional configuration mechanism.