AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.5.3. Timing Closure for FPGA Accelerators

The HPS bridges and FPGA-to-SDRAM interfaces exposed to the FPGA are synchronous and clock crossing is performed within the interface itself. As a result, you only need to ensure that both the FPGA-facing logic and your user design close timing in Timing Analyzer. Interrupts are considered asynchronous by the HPS, and as a result the HPS logic resynchronizes them to the internal HPS clock domain so there is no need to close timing for them.

Conduits carry signals that do not fit into any standard interface supported by Platform Designer (Standard). Examples of these are HPS peripheral external interfaces routed into the FPGA fabric or the HPS DMA peripheral request interfaces.