AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents
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3.6.6. Data Alignment for ACP and L2 Cache ECC accesses

The L2 cache performs error detection and correction in groups of 64 bits without the use of byte enables.

GUIDELINE: Accesses to the ACP must be 64-bit aligned, full 64-bit accesses, and no byte lanes can disabled on write.

The main L3 switch and the ACP port are both 64 bits wide, so it is only necessary to provide 64-bit aligned cache coherent accesses that are 64 bits wide after resizing.

Data resizing can occur in the L3 interconnect between requesting master and the ACP. As a result, a 32-bit access can be compatible with the L2 cache ECC logic if the access is aligned to 8-byte boundaries and the master performs bursts of size 2, 4, 8, or 16. Data resizing can also occur within the FPGA-to-HPS bridge.

GUIDELINE: The simplest way to ensure that accesses from the FPGA meets the L2 cache ECC requirements is to implement 64-bit masters in the FPGA fabric and configure the FPGA-to-HPS bridge to expose a 64-bit slave port. This ensures that no resizing of AXI* transactions is necessary. Full 64-bit accesses have to be made by the logic in the FPGA as well.