AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents Golden Hardware Reference Design

The Golden Hardware Reference Design is an Intel® Quartus® Prime project that contains a full HPS design for the Cyclone® V SoC / Arria® V SoC Development Kit. The GHRD has connections to a boot source, SDRAM memory and other peripherals on the development board.

For every new released version of SoC EDS, the GHRD is included in the SoC EDS tools. The GHRD is regression tested with every major release of the Intel® Quartus® Prime Design Software and includes the latest bug fixes for known hardware issues. The GHRD serves as a known good configuration of an SoC FPGA hardware system.

Figure 8.  Cyclone® V / Arria® V SoC Golden Hardware Reference Design Overview

The GHRD has a minimal set of peripherals in the FPGA fabric, because the HPS provides a substantial selection of peripherals. HPS-to-FPGA and FPGA-to-HPS interfaces are configured to a 64-bit data width.

GUIDELINE: Intel recommends that you use the latest GHRD as a baseline for new SoC FPGA hardware projects. You may then modify the design to suit your application ends.

The GHRD can be obtained from:
  • The GSRD for Linux page for the latest version, which is the best known configuration
  • <SoC EDS installation directory>\examples\hardware\cv_soc_devkit_ghrd - for the version supported by the corresponding SoC EDS version, used as a basis for the provided HWLibs design examples.