AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

5.4.2. System-Level ECC Control, Status and Interrupt Management

The System Manager contains a set of ECC-related registers for system-level control and status for all the ECC controllers in the HPS subsystem. ECC-related interrupts are also managed through this set of registers.