AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 18.0

The purpose of this document is to provide a set of design guidelines and recommendations, as well as a list of factors to consider, for designs that use the Cyclone® V SoC and Arria V SoC FPGA devices. This document assists you in the planning and early design phases of the SoC FPGA design, Platform Designer (Standard) sub-system design, board design and software application design.

Note: This application note does not include all the Cyclone® V/ Arria® V Hard Processor System (HPS) device details, features or information on designing the hardware or software system. For more information about the Cyclone® V or Arria® V HPS features and individual peripherals, refer to the respective Hard Processor System Technical Reference Manual.

Design guidelines for the FPGA portion of your design are provided in the Arria V and Cyclone V Design Guidelines.