1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs 2. Background: Comparison between Cyclone® V SoC FPGA and Arria® V SoC FPGA HPS Subsystems 3. Design Guidelines for HPS portion of SoC FPGAs 4. Board Design Guidelines for SoC FPGAs 5. Embedded Software Design Guidelines for SoC FPGAs A. Support and Documentation B. Additional Information
22.214.171.124. Boot Source 126.96.36.199. Select Desired Flash Device 188.8.131.52. BSEL Options 184.108.40.206. Boot Clock 220.127.116.11. CSEL Options 18.104.22.168. Selecting NAND Flash Devices 22.214.171.124. Determine Flash Programming Method 126.96.36.199. For QSPI and SD/MMC/eMMC Provide Flash Memory Reset 188.8.131.52. Selecting QSPI Flash Devices
4.5.1. HPS EMAC PHY Interfaces 4.5.2. USB Interface Design Guidelines 4.5.3. QSPI Flash Interface Design Guidelines 4.5.4. SD/MMC and eMMC Card Interface Design Guidelines 4.5.5. NAND Flash Interface Design Guidelines 4.5.6. UART Interface Design Guidelines 4.5.7. I2C Interface Design Guidelines 4.5.8. SPI Interface Design Guidelines
5.1.1. Assembling the Components of Your Software Development Platform 5.1.2. Selecting an Operating System for Your Application 5.1.3. Assembling your Software Development Platform for Linux 5.1.4. Assembling a Software Development Platform for a Bare-Metal Application 5.1.5. Assembling your Software Development Platform for a Partner OS or RTOS 5.1.6. Choosing Boot Loader Software 5.1.7. Selecting Software Tools for Development, Debug and Trace
184.108.40.206. Enable Runtime Calibration Report 220.127.116.11. Change DLEVEL To Get More Debug Information 18.104.22.168. Enable Example Driver for HPS SDRAM 22.214.171.124. Change Data Pattern in Example Driver 126.96.36.199. Example Code to Write and Read from All Addresses 188.8.131.52. Read/Write to HPS Register in Preloader 184.108.40.206. Check HPS PLL Lock Status in Preloader
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
|Intel® Quartus® Prime Design Suite 18.0|
The purpose of this document is to provide a set of design guidelines and recommendations, as well as a list of factors to consider, for designs that use the Cyclone® V SoC and Arria V SoC FPGA devices. This document assists you in the planning and early design phases of the SoC FPGA design, Platform Designer (Standard) sub-system design, board design and software application design.
Note: This application note does not include all the Cyclone® V/ Arria® V Hard Processor System (HPS) device details, features or information on designing the hardware or software system. For more information about the Cyclone® V or Arria® V HPS features and individual peripherals, refer to the respective Hard Processor System Technical Reference Manual.
Design guidelines for the FPGA portion of your design are provided in the Arria V and Cyclone V Design Guidelines.
The SoC FPGA Designer’s Checklist
Overview of HPS Design Guidelines for SoC FPGA design
Overview of Board Design Guidelines for SoC FPGA Design
Overview of Embedded Software Design Guidelines for SoC FPGA Design
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