AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Public
Document Table of Contents

5.3. SD Card Low Power Mode Design Considerations

The SD/MMC Controller has a low power mode which is enabled by setting the cclk_low_power bit of the clkena register to 1. When this mode takes effect, the clock to the card is disabled when the card is idle for at least eight card clock cycles.

During this low power mode, the state of the SD I/O signals are as follows:
  • SD_CLK = 0
  • SD_CMD = 1
  • SD_D0..3 = floating
If the end application requires all SD I/O signals to be floating during the low power mode, the following procedure is recommended:
  1. When the card is not in use, after the last command:
    • Set the GPIOs associated to the SD_CMD and SD_CLK pins as inputs by using the gpio registers.
    • Change the pin muxing for the SD_CLK and SD_CMD pins to be GPIO signals by using the sysmgr.pinmux registers2.
  2. When the card is to be used again, before the next command:
    • Change back the pin muxing for the SD_CLK and SD_CMD to be SD I/O signals by using the sysmgr.pinmux registers.
Note:
When the SD/MMC controller is in reset state, the state of the SD I/O signals is as follows:
  • SD_CLK = 0
  • SD_CMD = floating
  • SD_D0..3 = floating