4.5.3. QSPI Flash Interface Design Guidelines
Up to four QSPI chip selects can be used with Cyclone® V/ Arria® V SoC. The device can boot only from QSPI connected to the chip select zero.
GUIDELINE: Ensure that the QSPI_SS signals are used in numerical order.
Intel® Quartus® Prime assumes that the QSPI_SS signals are used in order. It is not possible to use SS0 and SS2, for example, without using SS1.
GUIDELINE: If your design uses QSPI flash with 4-byte addressing, design the board to ensure that the QSPI flash is reset or power-cycled whenever the HPS is reset.
The HPS boot ROM on Cyclone V and Arria V runs in 3-byte address mode by default. If the QSPI flash is switched to 4-byte addressing during operation, ensure that it is returned to its default 3-byte addressing mode whenever the HPS is reset. Otherwise, the HPS cannot boot from or access the QSPI flash memory device.
You can switch the QSPI to 3-byte addressing mode using one of the following methods:
- If the QSPI device has a reset pin, assert the reset signal every time the HPS device is reset.
- If the QSPI device does not have a reset pin, power-cycle the QSPI device every time the HPS device is reset.
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