AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

5.5.1. Using the Preloader To Debug the HPS SDRAM

To debug the HPS EMIF, you can change the settings in the preloader to enable runtime calibration report, debug level information and check the status of HPS SDRAM PLL.

Note: Refer to "Building the Second Stage Bootloader" in the Intel® SoC FPGA Embedded Development Suite User Guide for step-by-step instructions for compiling the preloader.