AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents RGMII

Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. RGMII uses four-bit wide transmit and receive datapaths, each with its own source synchronous clock. All transmit data and control signals are source synchronous to TX_CLK, and all receive data and control signals are source synchronous to RX_CLK.

For all speed modes, TX_CLK is always sourced by the MAC, and RX_CLK is always sourced by the PHY. In 1000 Mbps mode, TX_CLK and RX_CLK are 125 MHz, and Dual Data Rate (DDR) signaling is used. In

10 Mbps and 100 Mbps modes, TX_CLK and RX_CLK are 2.5 MHz and 25 MHz, respectively, and rising edge Single Data Rate (SDR) signaling is used.

Figure 5. RGMII

I/O Pin Timing

This section addresses RGMII interface timing from the perspective of meeting requirements in the 1000 Mbps mode. The interface timing margins are most demanding in 1000 Mbps mode, thus it is the only scenario we consider here.

At 125 MHz, the period is 8 ns, but because both edges are used, the effective period is only 4 ns. The TX and RX busses are completely separate and source synchronous, simplifying timing. The RGMII spec calls for CLK to be delayed from DATA at the receiver in either direction by a minimum 1.0 ns and a maximum 2.6 ns.

In other words, the TX_CLK from the MAC to the PHY must be delayed from the output to the PHY input and the RX_CLK from the PHY output to the MAC input. The signals are transmitted source synchronously within the +/-500 ps RGMII skew spec in each direction as measured at the output pins. The minimum delay needed in each direction is 1ns but it is recommended to target a delay of 1.5 ns to 2 ns to keep timing margin.

Transmit path setup/hold

Only setup and hold for TX_CLK to TX_CTL and TXD[3:0] matter for transmit. The Cyclone® V/ Arria® V HPS Dedicated I/O does not feature programmable delay.

For TX_CLK from the Cyclone® V/ Arria® V SoC, you must introduce the 1.0 ns PHY minimum input setup time in the RGMII spec. It is strongly recommended to increase this to delay to 1.5 ns to 2.0 ns. Many PHYs offer programmable skew, and some support RGMII 2.0 which defaults to skew enabled on both transmit and receive datapaths.

Between PHY delay and FPGA I/O delay features, you must ensure either 2 ns of delay to CLK versus CTL and D[3:0] or 1.2 ns typical minimum setup skew typical of most PHYs. Consult the datasheet for your PHY vendor for more details.

GUIDELINE: Ensure your design includes the necessary Quartus settings to configure the HPS EMAC outputs for the required delays.

On the Cyclone® V/ Arria® V SoC Development Kit and the associated Golden Hardware Reference Design (the GHRD is the hardware component of the GSRD) PHY skew is implemented with the Microchip* (Micrel*) KSZ9021RN PHY. Refer to the hps_common_board_info.xml file and PHY driver code in the Golden System Reference Design (GSRD).

Receive path setup/hold

Only setup and hold for RX_CLK to RX_CTL and RXD[3:0] are necessary to consider for receive timings. For Cyclone® V/ Arria® V SoC HPS Dedicated I/O no other consideration on the PHY side or board trace delay is required.

GUIDELINE: Hardware developers should specify the required FPGA skew so that software developers can add the skew to the device driver code.

The hps_common_board_info.xml file is used to compile the Linux device tree for the Cyclone® V or Arria® V SoC GSRD.