AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Public
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4.5.5. NAND Flash Interface Design Guidelines

GUIDELINE: Ensure that the selected NAND flash device is an 8-bit ONFI 1.0 (or later) compliant device.

The NAND flash controller in the HPS requires:
  • The external flash device to be 8-bit ONFI 1.0 compliant
  • Single-level cell (SLC) or multi-level cell (MLC)
  • Page size: 512 bytes, 2 KB, 4 KB or 8 KB
  • Pages per block: 32, 64, 128, 256, 384 or 512
  • Error correction code (ECC) sector size can be programmed to 512 bytes (for 4-, 8- or 16-bit correction) or 1024 bytes (24-bit correction)

You cannot export the NAND interface to FPGA.

Note: Refer to Supported Flash Devices for Cyclone® V and Arria® V SoC for a list of supported NAND devices.