AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

5.5.2. Access HPS SDRAM via the FPGA-to-SDRAM Interface

The HPS bridges can be enabled from the Preloader (SPL/MPL) or U-Boot and in some cases from Linux.

Note: Preloaders (SPL) and U-Boot generated from SoC EDS 13.1 and later contain extra functionality and built in functions to safely enable the HPS bridges.

To enable the HPS FPGA-to-SDRAM bridge from the Preloader or U-Boot, follow the appropriate steps.

Enabling HPS-to-FPGA Bridges from the Preloader

The Preloader checks the status of the FPGA and automatically enables bridges configured in Platform Designer (Standard) and the BSP if the FPGA is configured. The Preloader supports programming the FPGA before running automatic bridge enable tests and code.

For more information, refer to GSRD v13.1 - Programming FPGA from HPS.

Enabling HPS-to-FPGA Bridges from U-Boot

The bridge_enable_handoff command can be run from the U-boot command prompt to enable bridges. This command puts the HPS and SDRAM into a safe state before enabling all bridges after appropriate checks.

For more information, refer to the KDB solution: How can I enable the FPGA2SDRAM bridge on Cyclone® V SoC and Arria® V SoC Devices?