AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents Adapting to SGMII

It is possible to adapt the GMII HPS EMAC PHY signals to an SGMII PHY interface at the FPGA transceiver I/O pins using logic in the FPGA and the multi-gigabit transceiver I/O. While it is possible to design custom logic for this adaptation, this section describes using Platform Designer (Standard) adapter IP.

GUIDELINE: Use the Intel® HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge, available in Platform Designer (Standard).

Configure the HPS component in Platform Designer (Standard) for an EMAC as “FPGA” I/O instance. Do not export the resulting HPS component GMII signals in Platform Designer (Standard). Instead, add the Intel® HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge to the Platform Designer (Standard) subsystem and connect to the HPS component’s GMII signals. The bridge uses the Intel® HPS EMAC Interface Splitter in Platform Designer (Standard) to split out the emac conduit from the HPS component for use by the GMII bridge. The bridge instantiates the Intel® Triple Speed Ethernet (TSE) MAC, configured in 1000 BASE-X/SGMII PCS PHY-only mode (i.e., no soft MAC component). See the Embedded Peripherals IP User Guide for information on how to use the Intel® HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge.

Note: Refer to the Cyclone® V SGMII Example Design for hardware and software example of this implementation.