AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.3.2. Early Pin Planning and I/O Assignment Analysis

GUIDELINE: Choose an I/O voltage level for the HPS Dedicated Function I/O

HPS_CLK1, HPS_CLK2, HPS_nPOR and HPS_nRST are powered by VCCRSTCLK_HPS. These HPS Dedicated Function Pins are LVCMOS/LVTTL at either 3.3V, 3.0V, 2.5V or 1.8V. The I/O signaling voltage for these pins are determined by the supply level applied to VCCRSTCLK_HPS.

Note: HPS_PORSEL can be connected to either VCCRSTCLK_HPS (for fast HPS POR delay) or GND (for standard HPS POR delay).
Note: VCCRSTCLK_HPS can share the same power and regulator with VCCIO_HPS and VCCPD_HPS if they share the same voltage requirement. The functionality of powering down the FPGA fabric, while keeping the HPS running, is not needed.