5.4.3. ECC for L2 Cache Data Memory
The L2 cache memory is ECC protected, while the tag RAMs are parity protected. L2 cache ECC is enabled through a control register in the System Manager.
- “Single Event Upset Protection”
- “L2 Cache Controller Address Map for Cyclone® V” or "L2 Cache Controller Address Map for Arria® V"
GUIDELINE: The L1 and L2 cache must be configured as write-back and write-allocate for any cacheable memory region with ECC enabled.
For BSPs supported by the Intel® SoC FPGA EDS, you can configure your BSP for ECC support with the bsp-editor utility.
For bare metal firmware, refer to "L2 Cache Controller Address Map" in the " Cortex®-A9 Microprocessor Unit Subsystem" chapter of the appropriate Hard Processor System Technical Reference Manual.
GUIDELINE: Cache-coherent accesses through the L3 interconnect using the ACP must perform 64-bit wide, 64-bit aligned write accesses when ECC is enabled in the L2 Cache Controller
Enabling ECC does not affect the performance of the L2 cache, but accesses using the ACP must be 64-bit wide, 64-bit aligned in memory. This includes FPGA masters accessing the ACP over the FPGA-to-HPS Bridge. For a list of possible combinations of bridge width and FPGA master width, alignment and burst size and length, refer to "FPGA-to-HPS Access to ACP" in the "HPS-FPGA Bridges" chapter of the appropriate Hard Processor System Technical Reference Manual.
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