AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Public
Document Table of Contents
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3.6.2. Coherency between FPGA Logic and HPS: Accelerator Coherency Port (ACP)

The accelerator coherency port (ACP) of the SCU provides a means for other masters in the system, including logic implemented in the FPGA fabric, to perform cache coherent accesses. Accesses to the ACP are only unidirectional in terms of cache coherency meaning at the time of the access the data is up to date, but the SCU is not responsible for maintaining coherency of that data over time. For example, if a master in the FPGA reads data from the ACP and then a processor updates that same data in memory, then the FPGA no longer contains the most up to date copy of the data.