AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents
Give Feedback Consider Desired HPS Boot Clock Frequency

Cyclone® V / Arria® V SoC devices support a HPS boot clock from 10-50 MHz in PLL bypass mode, and up to 400MHz in PLL Locked mode. During power up or cold reset, the boot ROM samples the value of the CSEL pins and if needed, configure the HPS PLL to provide a faster boot clock frequency.

Refer to the table with CSEL options and corresponding external oscillator frequency in the "Booting and Configuration" appendix of the appropriate Hard Processor System Technical Reference Manual.