AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.6.5. FPGA Access to ACP via AXI* or Avalon-MM

The AXI* protocol allows masters to issue cacheable accesses whereas the Avalon-MM protocol does not support this feature. For an FPGA master to perform a cacheable access, the master must adhere to the AXI* protocol and be able to perform cacheable accesses, with ARCACHE[1] or AWCACHE[1] set to 1 and ARUSER[0] or AWUSER[0] set to 1.