AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.6.1. Cache Coherency

There are several mechanisms via which coherency are maintained through the system:

The HPS maintains cache coherency at a level 1 memory subsystem level within the MPU subsystem. The snoop control unit (SCU) built into the MPU subsystem maintains cache coherency between the two L1 data caches using the modified-​exclusive-​shared-​invalid (MESI) coherency protocol.