126.96.36.199. Initial Conditions and Hyper-Registers
If you must rely on initial conditions, and your system requires that all registers start synchronously, the use of clock gating is recommended. Because Hyper-Registers lack a reset or enable signal, you cannot initialize them to a specific value using a reset control signal. Intel® Stratix® 10 Hyper-Registers can power up to 0 or 1. Intel® Agilex™ Hyper-Registers power up to 1 during configuration. When the system starts up, right after configuration, the initial values are present without the need for an explicit reset.
Clock Gating For ALM and Hyper-Registers
Independent signals drive the internal clock controls of ALM registers and Hyper-Registers in Intel® Hyperflex™ architecture FPGAs. During the configuration process, the registers become active row by row (as opposed to device wide). In addition, ALM register clocks can potentially enable independently from Hyper-Register clocks. If the design clock is free running, this can cause potential race conditions between rows and between ALM registers and Hyper-Registers. These conditions can result in potential overwrite of initial conditions. To avoid these scenarios, gate the clock until after all clock controlling logic de-asserts, and all registers are active.