Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Public
Document Table of Contents

5.2.4.1. Example of Loops Limiting the Critical Chain

The following screenshots show the relevant panels from the Fast Forward Details report and the logic contained in the critical chain.

Figure 116. Fast Forward Details Report showing Limiting Reason for Hyper-Optimization is a Loop

In Figure 117, the Register ID for the start and end points is the same, which is #1. This case indicates that the start and end points of the chain are the same, thereby creating a loop.

Figure 117. Critical Chain with Loop (lines 1-34)
Figure 118. Critical Chain with Loop (lines 35-65)

Figure 119 shows the output of the Addr_wr[0] register feeding back to its enable input through eight levels of combinational logic.

Figure 119. Critical Chain in Technology Map Viewer

The figure does not show the other inputs to the logic cone for the Addr_wr[0] register. Source Code for Critical Chain shows portions of the source, and some inputs to the Addr_wr registers.

Source Code for Critical Chain

assign          Add_wr_pluse        =Add_wr+1;
assign          Add_wr_pluse_pluse  =Add_wr+4;

always @ (Add_wr_pluse or Add_rd_ungray)
    if (Add_wr_pluse==Add_rd_ungray)
        Full    =1;
    else
        Full    =0;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr  <= 0;
    else if (Wr_en&&!Full)
        Add_wr  <= Add_wr +1;

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