Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
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2.4. Hyper-Optimization (Optimize RTL)

After you accelerate data paths through Hyper-Retiming, Fast Forward compilation, and Hyper-Pipelining, the design may still have limits of control logic, such as long feedback loops and state machines.

To overcome such limits, use functionally equivalent feed-forward or pre-compute paths, rather than long combinatorial feedback paths. The following sections describe specific Hyper-Optimization for various design structures. This process can result in 2x performance gain for Intel® Hyperflex™ architecture FPGAs, compared to previous generation high-performance FPGAs.

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