Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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Document Table of Contents

10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History

Document Version Intel® Quartus® Prime Version Changes
2021.10.11 21.3
  • Removed obsolete Hyper-Retimer Readiness Rules topic. These rules are now in other rule categories.
  • Replaced missing figure in Step 2: Instantiate the Variable Latency Module topic.
2021.10.04 21.3
  • Revised Step 2: Instantiate the Variable Latency Module with explanation on partition boundary limits, correct use of constraints, and illustrations.
2021.06.21 20.1
  • Added links to Intel® Agilex™ Device Datasheet and Intel® Stratix® 10 Device Datasheet.
2020.07.13 20.1
  • Changed reference from asynchronous reset to synchronous reset in reference to "Retiming Example – Second Register Pushes out of ALM" figure.
  • Updated "Initial Power-Up Conditions" section to reflect latest IP and default state of QSF options.
  • Removed obsolete "Synchronous Start System Clock Gating Examples" topic.
2020.05.01 20.1
  • Added "Clock Domain Crossing Constraint Guidelines" topic.
  • Added Synchronization Register Chain Length assignment details to "Metastability Synchronizers" topic.
2019.12.16 19.4.0
  • Referenced programming file generation support for Intel® Agilex™ devices.
  • Added details, example, and table to "Preserving Registers During Synthesis" topic.
  • Added note and links about reset release requirement to "Reset Strategies" topic.
  • Added "Compiling Submodules Independently" topic.
2019.11.15 19.3.0
  • Added note about assignment precedence to "Specifying a Latency-Insensitive False Path."
  • Clarified insertion of vlat module in "Step 2: Instantiate the Variable Latency Module."
2019.11.04 19.3.0
  • Retitled document from Intel® Stratix® 10 High-Performance Design Handbook and updated throughout to include Intel® Agilex™ devices.
  • Added "Design Rule Checking with Design Assistant" topic.
  • Added "Running Design Assistant During Compilation" topic.
  • Added "Running Design Assistant in Analysis Mode" topic.
  • Added "Cross-Probing from Design Assistant" topic.
  • Added "Running Design Assistant from Chip Planner" topic.
  • Added "Running Design Assistant from Timing Analyzer" topic.
  • Added "Hyper-Retimer Readiness Rules" topic and link to specific rule descriptions.
2019.07.01 19.2.0
  • Improved quality of various screenshots.
  • Updated "Step 1; Compile the Base Design" with results.
  • Added more detail about the purpose of adding the 5 pipeline stages to "Step 2: Add Pipeline Stages and Remove Asynchronous Resets."
  • Minor wording changes and updated figure and table references throughout.
  • Updated link to design example files.
  • Updated diagrams in "Synchronous Resets and Limitations" topic.
2018.12.30 18.1.0
  • Added description of variable latency auto pipelining feature.
  • Updated new section on "Initial Conditions and Hyper-Registers."
  • Added new "Synchronous Start System Example" topic.
  • Added new "Implementing Clock Gating" topic.
2018.10.04 18.0.0
  • Minor text change in "Fast Forward Limit."
  • Minor text change in "Delay Lines."
2018.10.01 18.0.0
  • Corrected typo in "Retiming through RAMs and DSPs."
2018.07.12 18.0.0
  • Updated all code templates in Appendix A: Parameterizable Pipeline Modules.
  • Added Dual Clock Skid Buffer Example to Flow Control with Skid Buffers topic.
  • Updated various screenshots for improved visibility and accuracy of results.
2018.06.22 18.0.0 Corrected error in Original Loop Structure diagram in Loop Pipelining Demonstration.
2018.05.22 18.0.0
  • Retitled Removing Asynchronous Clears to Removing Asynchronous Resets.
  • Converted code images to code examples and corrected code syntax in Removing Asynchronous Resets.
  • Updated signal names in Removing Asynchronous Resets images to match code examples.
  • Corrected syntax error in Shannon's Decomposition Example.
  • Moved information about flow control with skid buffers into new Flow Control with Skid Buffers topic.
  • Enhanced description of FIFO Flow Control Loop with Two Skid Buffers diagram.
  • Clarified description of Improved FIFO Flow Control Loop with Almost Full instead of Full FIFO diagram.
2018.05.07 18.0.0
  • Removed references to dont_touch synthesis attribute.
  • Added Retiming through RAMs and DSPs topic and diagrams.
  • Clarified use of preserve_syn_only synthesis attribute
  • Updated Intel® Quartus® Prime Pro Edition screenshots.
  • Corrected syntax errors in Round Robin Scheduler examples.
  • Updated description of Retime stage to include traditional register retiming.
2018.02.05 17.1.1 Updated link to Median Filter design examples files.




2017.11.06 17.1.0
  • Revised Design Example Walkthrough steps and results.
  • Provided link to available design example files for each stage.
  • Moved step-by-step design compilation instructions to Design Compilation chapter, Intel® Quartus® Prime Pro Edition Handbook.
  • Added Ternary Adders topic and examples.
  • Added Loop Pipelining topic and examples.
  • Added description of Reset Sequence Requirement report.
  • Updated for latest Intel® branding conventions.
2017.05.08 Quartus® Prime Pro v17.1 Stratix® 10 ES Editions
  • Updated software support version to Quartus® Prime Pro v17.1 Stratix® 10 ES Editions.
  • Added Initial Power-Up Conditions topic.
  • Added Retiming Reset Sequences topic.
  • Added guidelines for high-speed clock domains.
  • Added Fitter Overconstraints topic.
  • Described Hold Fix-up in Fitter Finalize stage.
  • Added statement about Fast Forward compilation support for retiming across RAM and DSP blocks.
  • Added details on coherent RAM to read-modify-write memory description.
  • Added description of Fast Forward Viewer and Hyper-Optimization Advisor.
  • Added Advanced HyperFlex Settings topic.
  • Added Prevent Register Retiming topic.
  • Added Preserve Registers During Synthesis topic.
  • Added Fitter Commands topic.
  • Added Finalize Stage Reports topic.
  • Replaced command line instructions with new GUI steps in compilation flows.
  • Described concurrent analysis controls in Compilation Dashboard.
  • Consolidated duplicate content and grouped Appendices together.
  • Updated diagrams and screenshots.
2016.08.07 2016.08.07
  • Added clock crossing and initial condition timing restriction details.
  • Described true dual-port memory support and memory width ratio with examples
  • Updated code samples and narrative in Design Example Walk-through
  • Added reference to provided Design Example files
  • Re-branded for Intel®
  • Updated for latest changes to software GUI and capabilities.
2016.03.16 2016.03.16 First public release.