Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Document Table of Contents Retiming Reset Sequences

Under certain conditions, the Retime stage performs transformation of registers with a c-cycle value greater than zero. This ability can help improve the maximum frequency of the design. However, register retiming with a c-cycle equivalence value greater than zero requires extra precaution to ensure functional equivalence after retiming. To retain functional equivalence, reuse existing reset sequences, and add the appropriate number of clock cycles, as the following sections describe:

Modifying the Reset Sequence

Follow these recommendations to maximize operating frequency of resets during retiming:
  • Remove sclr signals from all registers that reset naturally. This removal allows the registers to move freely in the logic during retiming.
  • Make sure that the ALLOW_POWER_UP_DONT_CARE global assignment is set to ON. This setting maximizes register movement.
  • Compute and add to the reset synchronizer the relevant amount of extra clock cycles due to c-cycle equivalence.

Adding Clock Cycles to Reset

The Compiler reports the number of clock cycles to add to your reset sequence in the Fitter > Retime Stage > Reset Sequence Requirement report. The report lists the number of cycles to add on a clock domain basis.

Figure 20. Reset Sequence Requirement Report

Register duplication into multiple branches has a c-cycle of 1. Regardless of the number of duplicate registers, the register is always one connection away from its original source. After one clock cycle, all the branches have the same value again.

The following examples show how adding clock cycles to the reset sequence ensures the functional equivalence of the design after retiming.

Pipelining and Register Duplication shows pipelining of registers with potential for forward retiming. The c-cycle value equals 0.

Figure 21. Pipelining and Register Duplication

Impact of One Register Move shows a pipelining of registers after forward retiming of one register. Because the c-cycle value equals 1, the reset sequence for this circuit requires one additional clock cycle for functional equivalence after reset.

Figure 22. Impact of One Register Move

Impact of Two Register Moves shows a pipelining of registers after forward retiming of two registers. Because the c-cycle value equals 2, the reset sequence for this circuit requires two additional clock cycles for functional equivalence after reset.

Figure 23. Impact of Two Register Moves

Each time a register from the pipeline moves into the logic, the register duplicates and the C-cycle value of the design increases by one.

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