Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
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2.3.2.2.1. Step 1: Create the Variable Latency Module

You can use the Hyper-Pipelining Variable Latency Module template (hyperpipe_vlat), available in the Intel® Quartus® Prime software, to create the variable latency module for use in automatic pipeline insertion.

The hyperpipe_vlat module contains a single pipeline stage. The Hyper-Retimer adds the same number of pipeline stages to all the bits in one instance of the hyperpipe_vlat module. The module includes the following customizable parameters:

  • WIDTH—specifies the width of the bus, with a default value of one.
  • MAX_PIPE—specifies the maximum number of pipeline stages the Hyper-Retimer can add at that instance. The value must be between 1 and 100, inclusive. The default value is 100.
Hyper-Pipelining Variable Latency Module Templates

Follow these steps in the Intel® Quartus® Prime software to create a variable latency module:

  1. Click File > New and create a new Verilog HDL or VHDL design file.
  2. Right-click in the new file, and then click Insert Template.
  3. Select the Verilog HDL (or VHDL) > Full Designs > Pipelining > Hyper-Pipelining Variable Latency Module, and then click Enter and Close. The module template inserts into the file.
  4. Specify appropriate values for the WIDTH and MAX_PIPE parameters when you instantiate the hyperpipe_vlat module.
  5. Save the file.

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