Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Clock Domain Crossing Constraint Guidelines

You must apply appropriate timing constraints to any multi-bit clock domain crossing. The set_false_path constraint has a higher precedence than all other path-based constraints. Therefore, when a clock domain crossing has a set_false_path constraint, timing analysis can ignore other lower precedence constraints like skew.

Follow these guidelines to properly constrain a clock domain crossing:

  • Review the SDC timing constraints to ensure that no set_false_path constraint exists between the two clock domains.
  • To remove any false paths between two clock domains from setup and hold timing analysis, apply the set_clock_groups constraint, rather than set_false_path constraint. set_clock_groups has a lower precedence than set_false_path.
  • Constrain the paths between the two clock domains with set_net_delay to make the nets as short as possible.
  • Constrain the nets between the two clock domains with set_max_skew. You can view the results in comparison to your constraint in the Timing Analyzer reports.

The following shows example constraints for a clock domain crossing between data_a in clk_a clock domain, and data_b in clk_b clock domain:

create_clock -name clk_a -period 4.000 [get_ports {clk_a}]
create_clock -name clk_b -period 4.500 [get_ports {clk_b}]
set_clock_groups -asynchronous -group [get_clocks {clk_a}] -group \
     [get_clocks {clk_b}]
set_net_delay -from [get_registers {data_a[*]}] -to [get_registers \
     {data_b[*]}] -max -get_value_from_clock_period dst_clock_period \
     -value_multiplier 0.8
set_max_skew -from [get_keepers {data_a[*]}] -to [get_keepers {data_b[*]}] \
     -get_skew_value_from_clock_period src_clock_period \
     -skew_value_multiplier 0.8