Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
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2.4.2.1.3. Viewing Clocks in the Timing Analyzer

The Timing Analyzer reports high speed clocks that are limited by long clock paths. Open the Fmax Summary report to view any clock fMAX that is restricted by high minimum pulse width violations (tCH), or low minimum pulse width violation (tCL).

To view clock network data in the Timing Analyzer:

  1. Open a project.
  2. On the Compilation Dashboard, click Timing Analysis. After timing analysis is complete, the Timing Analyzer folder appears in the Compilation Report.
  3. Under the Slow 900mV 100C Model folder, click the Fmax Summary report.
  4. To view path information details for minimum pulse width violations, in the Compilation Report, right-click the Minimum Pulse Width Summary report and click Generate Report in Timing Analyzer. The Timing Analyzer loads the timing netlist.
  5. Click Reports > Custom Reports > Report Minimum Pulse Width.
  6. In the Report Minimum Pulse Width dialog box, specify options to customize the report output and then click OK.
  7. Review the data path details for report of long clock routes in the Slow 900mV 100C Model report.
    Figure 62. Minimum Pulse Width Details Show Long Clock Route

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