Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
Document Table of Contents

2.1.1.2. Speed and Latency

The following table illustrates the rate of growth for various types of circuits as the bus width increases. The circuit functions interleave with big O notations of area as a function of bus width, starting at sub-linear with log(N), to super-linear with N*N.
Table 2.  Effect of Bus Width on Area
  Circuit Function
Bus Width (N) log N Mux ripple add N*log N barrel shift Crossbar N*N
16 4 5 16 64 64 80 256
32 5 11 32 160 160 352 1024
64 6 21 64 384 384 1344 4096
128 7 43 128 896 896 5504 16384
256 8 85 256 2048 2048 21760 65536

Typically, circuit components use more than 2X the area as the bus width doubles. For a simple circuit like a mux, the area grows sub-linearly as the bus width increases. Cutting the bus width of a mux in half provides slightly worse than linear area benefit. A ripple adder grows linearly as the bus width increases.

More complex circuits, like barrel shifters and crossbars, grow super-linearly as bus width increases. If you cut the bus width of a barrel shifter, crossbar, or other complex circuit in half, the area benefit can be significantly better than half, approaching quadratic rates. For components in which all inputs affect all outputs, increasing the bus width can cause quadratic growth. The expectation is then that, if you take advantage of speed-up to work on half-width buses, you generate a design with less than half the original area.

When working with streaming datapaths, the number of registers is a fair approximation of the latency of the pipeline in bits. Reducing the width by half creates the opportunity to double the number of pipeline stages, without negatively impacting latency. This higher performance generally requires significantly less than double the amount of additional registering to create a latency profit.

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