Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
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4.1.3. Step 3: Add More Pipeline Stages and Remove All Asynchronous Resets

The Fast Forward Timing Closure Recommendations suggest further changes that you can make to enable additional optimization during retiming. The Optimizations Analyzed tab reports the specific registers in the analysis for you to modify. The report indicates that state_machine.v still contains asynchronous resets that limit optimization. Follow these steps to remove remaining asynchronous resets in state_machine.v, and add more pipeline stages:
  1. Use the techniques and examples in Step 2: Add Pipeline Stages and Remove Asynchronous Resets to change all asynchronous resets to synchronous resets in state_machine.v. These resets are in multiple locations in the file, as the report indicates.
  2. In the Fast Forward Details report, select the last optimization row before the Fast Forward Limit row, and then click the Optimizations Analyzed tab. Optimizations Analyzed indicates the location and number of registers to add.
  3. Use the techniques and examples in Step 2: Add Pipeline Stages and Remove Asynchronous Resets to add the number of pipeline stages at the locations in the Optimizations Analyzed tab.
  4. Once again, compile the design and view the Fast Forward Details report. The performance increase is similar to the estimates, but short path and long path combinations still limit further performance. The next step addresses this performance limit.
    Note: As an alternative to completing the preceding steps, you can open and compile the Median_filter_<version>/Step_2/median.qpf project file that already includes these changes, and then observe the results.

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