1. Intel® Hyperflex™ FPGA Architecture Introduction 2. Intel® Hyperflex™ Architecture RTL Design Guidelines 3. Compiling Intel® Hyperflex™ Architecture Designs 4. Design Example Walk-Through 5. Retiming Restrictions and Workarounds 6. Optimization Example 7. Intel® Hyperflex™ Architecture Porting Guidelines 8. Appendices 9. Intel® Hyperflex™ Architecture High-Performance Design Handbook Archive 10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History
184.108.40.206. High-Speed Clock Domains 220.127.116.11. Restructuring Loops 18.104.22.168. Control Signal Backpressure 22.214.171.124. Flow Control with FIFO Status Signals 126.96.36.199. Flow Control with Skid Buffers 188.8.131.52. Read-Modify-Write Memory 184.108.40.206. Counters and Accumulators 220.127.116.11. State Machines 18.104.22.168. Memory 22.214.171.124. DSP Blocks 126.96.36.199. General Logic 188.8.131.52. Modulus and Division 184.108.40.206. Resets 220.127.116.11. Hardware Re-use 18.104.22.168. Algorithmic Requirements 22.214.171.124. FIFOs 126.96.36.199. Ternary Adders
5.2.1. Insufficient Registers 5.2.2. Short Path/Long Path 5.2.3. Fast Forward Limit 5.2.4. Loops 5.2.5. One Critical Chain per Clock Domain 5.2.6. Critical Chains in Related Clock Groups 5.2.7. Complex Critical Chains 5.2.8. Extend to locatable node 5.2.9. Domain Boundary Entry and Domain Boundary Exit 5.2.10. Critical Chains with Dual Clock Memories 5.2.11. Critical Chain Bits and Buses 5.2.12. Delay Lines
4.1.3. Step 3: Add More Pipeline Stages and Remove All Asynchronous Resets
The Fast Forward Timing Closure Recommendations suggest further changes that you can make to enable additional optimization during retiming. The Optimizations Analyzed tab reports the specific registers in the analysis for you to modify. The report indicates that state_machine.v still contains asynchronous resets that limit optimization. Follow these steps to remove remaining asynchronous resets in state_machine.v, and add more pipeline stages:
- Use the techniques and examples in Step 2: Add Pipeline Stages and Remove Asynchronous Resets to change all asynchronous resets to synchronous resets in state_machine.v. These resets are in multiple locations in the file, as the report indicates.
- In the Fast Forward Details report, select the last optimization row before the Fast Forward Limit row, and then click the Optimizations Analyzed tab. Optimizations Analyzed indicates the location and number of registers to add.
- Use the techniques and examples in Step 2: Add Pipeline Stages and Remove Asynchronous Resets to add the number of pipeline stages at the locations in the Optimizations Analyzed tab.
- Once again, compile the design and view the Fast Forward Details report. The performance increase is similar to the estimates, but short path and long path combinations still limit further performance. The next step addresses this performance limit.
Note: As an alternative to completing the preceding steps, you can open and compile the Median_filter_<version>/Step_2/median.qpf project file that already includes these changes, and then observe the results.
Did you find the information on this page useful?