Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Public

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2.2.7.1. Specifying Initial Memory Conditions

You can specify initial power-up conditions by inference in your RTL code. Intel® Quartus® Prime synthesis automatically converts default values for registered signals into Power-Up Level constraints. Alternatively, specify the Power-Up Level constraints manually.

Initial Power-Up Conditions Syntax (Verilog HDL)

reg q = 1’b1; //q has a default value of ‘1’
always @ (posedge clk)
begin
   q <= d;
end

Initial Power-Up Conditions Syntax (VHDL)

SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
PROCESS (clk, reset)
BEGIN
    IF (rising_edge(clk)) THEN
        q <= d;
    END IF;
END PROCESS;