ID 683353
Date 10/04/2021
Public

## 2.3.2.1.1. Specifying a Latency-Insensitive False Path

You can specify a latency-insensitive false path to allow the Hyper-Retimer to automatically add pipeline stages to a path. Specify latency-insensitive false paths only on cross-clock domain paths, such as between a low-speed configuration clock domain, and a high-speed data path clock domain, as in a signal processing design.

Specify the latency_insensitive option for the set_false_path exception to designate a false path as latency-insensitive. Specify the clock names for the from and to options, as the following example shows:

set_false_path -latency_insensitive -from  [get_clocks {clock_a}]  \
-to  [get_clocks {clock_b}]

Although not a syntax error to specify register, cell, net, pin, or keeper name for the from or to options, the Compiler interprets the false path as a retiming restriction, and prevents the Hyper-Retimer from retiming those endpoints. There is no benefit to using the latency_insensitive option on a register-to-register false path.

Note: The set_false_path constraint has higher precedence than all other path-based SDC constraints. If your latency-insensitive false path is on a clock domain transfer that includes FIFOs, bus synchronizers, or other cross-domain circuits that have path-based constraints (such as set_max_skew, set_max_delay, or set_min_delay), a clock-to-clock set_false_path constraint overrides these constraints. If you constrain a clock domain crossing with any path-based constraint, the latency_insensitive option overrides these constraints. Only use a latency-insensitive false path on clock domain crossing paths that you have actually cut from timing analysis.

In the following figure, the top diagram represents the design RTL, indicating the false path tagged as latency-insensitive false path. The bottom diagram shows how the Hyper-Retimer adds pipeline stages on the other side of the registers at endpoints of the latency-insensitive false path.

The Hyper-Retimer can add registers to the input of the source of the latency-insensitive false path, and to the output of the destination of the latency-insensitive false path. The Hyper-Retimer then retimes the registers backward and forward through the two clock domains.

Figure 32. Effect of Latency-Insensitive False Path on Circuit

The Hyper-Retimer analyzes the performance of each cross-clock-domain path separately to determine the number of stages to automatically add. The Hyper-Retimer may insert different numbers of stages on each cross-clock-domain path.

For example, a bus crossing a clock domain that is cut with the latency_insensitive option can have different latencies for each bit in the bus after the Hyper-Retimer runs. Therefore, ensure that the data crossing the clock domain remains constant for many clock cycles to ensure it becomes constant at the destination. For example, this can occur with a bus with different latencies on each bit.

The compilation report does not show the number of stages that the Hyper-Retimer inserts at a latency-insensitive false path. However, you can examine the connectivity in the timing netlist after the Hyper-Retimer finishes to determine the number of stages.