Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Public
Document Table of Contents

2.4.2.1.1. Visualizing Clock Networks

After running the Fitter, visualize clock network implementation in the Chip Planner. The Chip Planner shows the source clock pin location, clock routing, clock tree size, and clock sector boundaries. Use these views to make adjustment and reduce the total clock tree size.

To visualize design clock networks in the Chip Planner:

  1. Open a project.
  2. On the Compilation Dashboard, click Fitter, Early Place, Place, Route, or Retime to run the Fitter.
  3. On the Tasks pane, double-click Chip Planner. The Chip Planner loads device information and displays color coded chip resources.
  4. On the Chip Planner Tasks pane, click Report Clock Details. The Chip Planner highlights the clock pin location, routing, and sector boundaries. Click elements under the Clock Details Report to display general and fan-out details for the element.
  5. To visualize the clock sector boundaries, click the Layers Settings tab and enable Clock Sector Region. The green lines indicate the boundaries of each sector.
Figure 59. Clock Network in Chip Planner
Figure 60. Clock Sector Boundary Layer in Chip Planner

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