Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
Document Table of Contents

2.4.1.4. Loop Pipelining

Loops are omnipresent and an integral part of design functionality. However, loops are a limiting factor to Hyper-Retiming optimization. The Compiler cannot automatically pipeline any logic inside of a loop. Adding or removing a sequential element inside the loop potentially breaks the functionality of the design.

However, you can modify the loop structure to allow the Compiler to insert pipeline stages, without changing the functionality of the design, as the following topics demonstrate. Properly pipelining a loop involves the following steps:

  1. Restructure loop and non-loop logic
  2. Manually add pipeline stages to the loop
  3. Cascade the loop logic

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