Intel® Hyperflex™ Architecture High-Performance Design Handbook

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ID 683353
Date 10/04/2021
Public
Document Table of Contents

2.4.2.9.3. Intel® Hyperflex™ Architecture Simple Dual-Port Memory Example

Using two simple dual-port memories can double the use of M20K blocks in the device. However, this memory structure can perform at a frequency up to 1 GHz. This frequency is not possible when using true dual-port memory with independent clocks in Intel® Hyperflex™ architecture FPGAs.

Figure 74. Simple Dual-Port Memory Implementation

You can achieve similar frequency results by inferring simple dual-port memory in RTL, rather than by instantiation in the Intel® Quartus® Prime IP parameter editor.

Simple Dual-Port RAM Inference

module simple_dual_port_ram_with_SDPs
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
		input [(DATA_WIDTH-1):0] wrdata,
		input [(ADDR_WIDTH-1):0] wraddr, rdaddr,
		input we_a, wrclock, rdclock,
		output reg [(DATA_WIDTH-1):0] q_a
);

// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];

always @ (posedge wrclock)
begin
		// Port A  is for writing only
		if (we_a)
		begin
		ram[wraddr] <= wrdata;
		end
end

always @ (posedge rdclock)
begin
// Port B is for reading only
begin
q_a <= ram[rdaddr];
end
end
endmodule

True Dual-Port RAM Behavior Emulation

module test (wrdata, wraddr, rdaddr_a, rdaddr_b, 
	clk_a, clk_b, we_a, q_a, q_b);
	
	input [7:0] wrdata;
	input clk_a, clk_b, we_a;
	input [5:0] wraddr, rdaddr_a, rdaddr_b;
	output [7:0] q_a, q_b;
	
	simple_dual_port_ram_with_SDPs myRam1 (
		.wrdata(wrdata),
		.wraddr(wraddr),
		.rdaddr(rdaddr_a),
		.we_a(we_a),
		.wrclock(clk_a), .rdclock(clk_b),
		.q_a(q_a)
		);

	simple_dual_port_ram_with_SDPs myRam2 (
		.wrdata(wrdata),
		.wraddr(wraddr),
		.rdaddr(rdaddr_b),
		.we_a(we_a),
		.wrclock(clk_a), .rdclock(clk_a),
		.q_a(q_b)
		);
		
endmodule

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