Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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2. Intel® Hyperflex™ Architecture RTL Design Guidelines

This chapter describes RTL design techniques to achieve the highest clock rates possible in Intel® Hyperflex™ architecture FPGAs. Intel® Hyperflex™ architecture FPGAs support maximum clock rates significantly higher than previous FPGA generations.
Note: Avoiding RTL design rule violations improves the reliability, timing performance, and logic utilization of your design. The Intel® Quartus® Prime software includes the Design Assistant design rule checking tool to help avoid design rule violations. These rules include Hyper-Retimer Readiness Rules (HRR) that specifically target Intel® Hyperflex™ architecture FPGA designs, as Design Assistant Design Rule Checking describes.