Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021

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Document Table of Contents Automatic Pipeline Insertion

Automatic pipeline insertion allows the Hyper-Retimer to insert a number of pipeline stages at a location you specify in your design. You can specify the maximum number of pipeline stages to insert at each particular register.
Figure 33. Typical Use of Variable Latency Module

The Intel® Quartus® Prime software includes the Variable Latency Module template (hyperpipe_vlat) that simplifies implementation. Alternatively, you can implement automatic pipeline insertion using a combination of .qsf assignments.

When you instantiate the hyperpipe_vlat module, and the Enable Auto-Pipelining (HYPER_RETIMER_ENABLE_ADD_PIPELINING) option remains enabled, the Hyper-Retimer adds the appropriate number of additional pipeline stages at the specified register during retiming, up to the maximum that you specify. This setting is enabled by default. Click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) to access this setting.

Figure 34. Variable Latency Module with Maximum of Ten Pipeline Stages

For example, if you specify a maximum of 10 pipeline stages, the Hyper-Retimer may determine that only three additional pipeline stages are necessary to maximize the timing performance. The Hyper-Retimer adds only the appropriate number of pipeline stages necessary.

Figure 35. Hyper-Retimer Adds Only Additional Stages Needed

You can specify different numbers of pipeline stages for separate instances of the hyperpipe_vlat module, as the following diagram illustrates:

Figure 36. Different Maximum Pipeline Stages Per Module

The following steps describe how to implement automatic pipeline insertion in detail:

Valid values for the maximum number of additional stages are 1 to 100, inclusive.