184.108.40.206. Automatic Pipeline Insertion
The Intel® Quartus® Prime software includes the Variable Latency Module template (hyperpipe_vlat) that simplifies implementation. Alternatively, you can implement automatic pipeline insertion using a combination of .qsf assignments.
When you instantiate the hyperpipe_vlat module, and the Enable Auto-Pipelining (HYPER_RETIMER_ENABLE_ADD_PIPELINING) option remains enabled, the Hyper-Retimer adds the appropriate number of additional pipeline stages at the specified register during retiming, up to the maximum that you specify. This setting is enabled by default. Click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) to access this setting.
For example, if you specify a maximum of 10 pipeline stages, the Hyper-Retimer may determine that only three additional pipeline stages are necessary to maximize the timing performance. The Hyper-Retimer adds only the appropriate number of pipeline stages necessary.
You can specify different numbers of pipeline stages for separate instances of the hyperpipe_vlat module, as the following diagram illustrates:
The following steps describe how to implement automatic pipeline insertion in detail:
- Step 1: Create the Variable Latency Module
- Step 2: Instantiate the Variable Latency Module
- Step 3: Verify Automatic Pipeline Insertion Option
- (Optional) Auto-Pipeline Insertion without a Variable Latency Module
Valid values for the maximum number of additional stages are 1 to 100, inclusive.
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