Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 10/04/2021
Public
Document Table of Contents

1. Intel® Hyperflex™ FPGA Architecture Introduction

Updated for:
Intel® Quartus® Prime Design Suite 21.3
This document describes design techniques to achieve maximum performance with the Intel® Hyperflex™ FPGA architecture. The Intel® Hyperflex™ FPGA architecture supports Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization design techniques that enable the highest clock frequencies in Intel® Stratix® 10 and Intel® Agilex™ devices.
Intel® Hyperflex™ Architecture FPGAs
Intel® Hyperflex™ Architecture Devices Intel® Hyperflex™ Architecture Description
Intel® Stratix® 10 FPGAs

A "registers everywhere” architecture that packs bypassable Hyper-Registers into routing segments in the device core, and at all functional block inputs. The routing signal can travel through the register first, or bypass the register direct to the multiplexer, improving bandwidth and area and power efficiency.

Intel® Agilex™ FPGAs
Figure 1. Registers Everywhere
Figure 2. Bypassable Hyper-Registers

This document provides specific design guidelines, tool flows, and real world examples to take advantage of the Intel® Hyperflex™ FPGA architecture: