1. Intel® Hyperflex™ FPGA Architecture Introduction
|Intel® Quartus® Prime Design Suite 21.3|
|Intel® Hyperflex™ Architecture Devices||Intel® Hyperflex™ Architecture Description|
|Intel® Stratix® 10 FPGAs||
A "registers everywhere” architecture that packs bypassable Hyper-Registers into routing segments in the device core, and at all functional block inputs. The routing signal can travel through the register first, or bypass the register direct to the multiplexer, improving bandwidth and area and power efficiency.
|Intel® Agilex™ FPGAs|
This document provides specific design guidelines, tool flows, and real world examples to take advantage of the Intel® Hyperflex™ FPGA architecture:
- Intel Hyperflex Architecture RTL Design Guidelines—describes fundamental high-performance RTL design techniques for Intel® Hyperflex™ FPGA architecture designs.
- Compiling Intel Hyperflex Architecture Designs—describes how to use the Intel® Quartus® Prime Pro Edition software to get the highest performance with Intel® Hyperflex™ architecture FPGAs.
- Optimization Example—demonstrates performance improvement techniques using real world design examples.
- Intel Hyperflex Architecture Porting Guidelines—provides guidance for design migration to Intel® Hyperflex™ architecture FPGAs.